1. Field of the Invention
Embodiments of the present invention relate to circuit simulators and analysis of circuits. More specifically, embodiments of the present invention relate to a technique for estimating an output load on a logic gate.
2. Related Art
In circuit simulations or timing analysis, one or more electrical characteristics of a logic gate may be a function of its output load. For example, the delay of a stage that includes a driver and a receiver is a function of the input capacitance of the receiver gate, which in turn is a function of the effective capacitance (Ceff) at the output of the receiver gate. Consequently, the delay of the logic gate can be accurately modeled if Ceff is accurately determined.
However, determining Ceff accurately typically involves detailed calculations based on the poles and zeros associated with interconnect parasitics using iterative computation techniques, which are time-consuming.
In an attempt to address this problem, existing circuit simulation software includes approximations for Ceff. For example, zero and a total capacitance (Ctotal) for the output load are used to define minimum and maximum values of Ceff in circuit simulations. However, these extremum values often result in simulated delays that are, respectively, too pessimistic or too optimistic (i.e., too large or too small).
Hence, there is a need for a simulation technique that approximates Ceff without the above-described problems.